2 AlphaServer GS60E Release Notes
Handling of PAL Mode Halts
If the system halts with either a double-error halt or a machine check while in PAL mode,
you can get information on the halt condition.
Two AlphaServer GS60E halt conditions require special consideration:
• Double-error halt, halt code 06
• Machine check while in PAL mode halt, halt code 07
A double-error halt occurs when a subsequent machine check occurs while a machine check is in
progress. A machine check while in PAL mode halt occurs when a CPU experiences a machine
check while executing in PAL mode. Following either of these events, continued system
operation is not possible. And since the hardware error state cannot be collected through normal
mechanisms, there may be no related system error log entry or operating system memory dump
file. As a result of this, the minimum hardware error state necessary to isolate the failure to its
root cause is captured by console and PAL firmware and stored in the CPU module’s nonvolatile
EEPROM (flashrom) halt area. Subsequently, during the diagnosis of a PAL mode halt, a show
eeprom halt SRM console command should be entered to retrieve this information. (This
command should be performed on each CPU module).
The AlphaServer GS60E SRM console provides a nonvolatile area in each processor module’s
EEPROM for the storage of halt frames. A halt frame is built upon the occurrence of a CPU
double-error halt or machine check while in PAL mode halt. For console version V5.5-12, the
EEPROM halt area provides space for the storage of two frames per CPU; the first two PAL
mode halt events are saved. Once two frames have been saved, it will be necessary to reinitialize
the EEPROM halt area to enable the storage of subsequent events. This may be accomplished
through the console clear eeprom halt command. The halt frame is timestamped with the
contents of the CPU Watch Chip TOY Clock registers. On OpenVMS systems, the TOY Clock
Year Register contains the year, in hex, since 1900 while, on Tru64 UNIX systems, this register
contains the year since 1952. Additionally, it should be realized that since the primary CPU is
used to maintain the system time, the watch chip registers on secondary CPU modules may not
contain the accurate time of year. Therefore, the timestamp contained within the halt frame for a
secondary CPU should NOT be used to determine the time of occurrence.
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