Compaq AlphaServer ES40 Información técnica descargar pdf (Pagina 373)

Registers D-15

Table D–6 ISUM Register Fields

Name Extent Type Description

Reserved [63:39]

EI[5:0] [38:33] RO External Interrupts

SL [32] RO Serial Line Interrupt

CR [31] RO Corrected Read Error Interrupts

PC[1:0] [30:29] RO Performance Counter Interrupts

PC0 when PC[0] is set.

PC1 when PC[1] is set.

SI[15:1] [28:14] RO Software Interrupts

Reserved [13:11]

ASTU, ASTS [10],[9] RO AST Interrupts

For each processor mode, the bit is

set if an associated AST interrupt is

pending. This includes the mode’s

ASTER and ASTRR bits and

whether the processor mode value

held in the IER_CM register is

greater than or equal to the value

for the mode.

Reserved [8:5]

ASTE, ASTK [4],[3] RO AST Interrupts

For each processor mode, the bit is

set if an associated AST interrupt is

pending. This includes the mode’s

ASTER and ASTRR bits and

whether the processor mode value

held in the IER_CM register is

greater than or equal to the value

for the mode.

Reserved [2:0]

1 2 ... 368 369 370 371 372 373 374 375 376 377 378 ... 443 444

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