Compaq AlphaServer DS20 Manual de usuario descargar pdf (Pagina 6)

Third-Generation Alpha Chip

The third generation of the Alpha microprocessor, the Alpha

21264, is a superscalar superpipelined implementation of the

Alpha architecture. The first offering of this chip was known as

EV6. These systems are offered with the EV67 chip (.28

micron) and the EV68 chip (.18 micron). Each chip has over

15.2 million transistors. In our discussion here, the Alpha

21264 designation applies to all variants of the chip.

Designed for performance, the Alpha 21264 achieves this goal by

carefully studied and simulated architectural and circuit analysis.

The 21264 memory system also enables the high performance

levels. On-chip and off-chip caches provide for very low latency

data access, which allows for very high bandwidth data access. (In

DS20E systems the size of the off-chip cache is 8 MB running at

222 MHz (dual data rate cache) for EV67 and 8 MB running at 278

MHz DDR for EV68.)

Internal to each chip is a 64-Kbyte instruction cache (I-cache)

and a 64-Kbyte data cache (D-cache).

• I-cache. 64 Kbytes, two-way set-associative, virtually

addressed cache with 64-byte blocks

• D-cache. 64 Kbytes, two-way set-associative, virtually

indexed, physically tagged, writeback cache with 64-byte

blocks

Chip Operation

Several key design choices were made in the chip architecture

to maximize performance: Four instructions are fetched each

cycle, and then how those instructions are handled boosts the

speed of execution. Register renaming assigns a unique storage

location with each write reference to a register, avoiding register

dependencies that can be a potential bottleneck to processor

performance.

Another design feature, out-of-order execution, permits

instructions to execute in an order different from the order that

the instructions are fetched. In effect, instructions execute as

soon as possible. This allows for faster execution since critical

path computations are started and completed as soon as

possible.

In addition, the Alpha 21264 employs speculative execution to

maximize performance. It speculatively fetches and executes

instructions even though it may not know immediately whether

the instruction will be on the final execution path. This is

particularly useful, for instance, when the 21264 predicts

branch directions and speculatively executes down the

predicted path. The sophisticated branch prediction in the

21264 coupled with the speculative and dynamic execution

extracts the most instruction parallelism from applications.

For more information about the chip, see:

http://www.compaq.com/alphaserver/download/ev6chip.pdf

Alpha 21264 Features

• Out-of-order instruction execution

• Large (64 Kbyte) on-chip data and instruction caches

• Improved branch prediction through intuitive execution

• Register renaming

• Increased bandwidth for high-speed access to second-level

cache and system memory

• Motion video instructions

• Square root and divide instructions

• All instructions are 32 bits long and have a regular

instruction format

• Floating-point unit, supports DIGITAL and IEEE floating-

point data types

• 80 integer registers, 64 bits wide

• 72 floating-point registers, 64 bits wide

Processor Module

An AlphaServer DS20E can have one or two CPU modules.

In addition to the Alpha 21264 chip, the CPU module has an

8-Mbyte second-level cache and a DC-to-DC converter with

heatsink that provides the required voltage to the Alpha chip.

Power-up diagnostics are in a flash ROM on the module.

Cooling of the microprocessor chip is provided by a fan on the

chip heatsink, as shown here.

PK0237

Processor Configuration Rules

The first CPU module is installed in CPU slot 0. The second

CPU is installed in CPU slot 1.

Processor Upgrade

Upgrading to faster processor modules requires setting a

switch on the system board.

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